I. TCON Board (Logic Board) Description

The logic board consists of three parts. The first part is the power management unit (PMU) with 12V input to generate the voltage required by FPGA, GAMA IC, LCD, connected with PC application for debugging and configuration through MCU via I2C interface; the second part is the main control unit, mainly including devices such as FPGA, SPI Flash, and encryption IC; the third part is the GAMA voltage generation unit, with the special configurable GAMA IC as the master IC, used to generate the GAMA voltage required by the screen, generally offering 12~16 lanes and debugged online via I2C interface.

II. TCON Board Input Standards

The V-by-one protocol is a signal transmission interface standard developed by THine Electornics (Japan) for flat panel displays, involving SerDes technology in addition to clock signal recovery and other technologies to raise the transmission speed to 3.75 Gbp per pair of wires. Thus, our current AL3 and EG4 devices are unable to receive V-by-one signals. The current mainstream 4K motherboards are basically equipped with V-by-one interfaces.

There are two LVDS standards, JEIDA and VESA, which are just different in RGB sorting. According to the LVDS standard, each group consists of 4 lanes of data and one lane of clock, clocked at 74.25 MHz, transmitting 7 bits per clock cycle at 519.75 Mbps. Both AL3 and EG4 devices can receive LVDS input.

III. TCON Board Output Standards

USI-T protocol is a standard proposed by Samsung dedicated to TV panel drive, which is currently used for most of 4K TV screens. According to the protocol, each pair of signals is independent and all need to contain information such as clock, video parameters, GAMA parameters, and pixel data, with the transmission speed at 600 Mbps~1.6 Gbps. AL3/EG4 chips can only be used for screens with low speed requirements.

According to the mini-lvds protocol, each group generally consists of 1 lane of clock and 6 lanes of data. The clock frequency is adjusted according to the amount of data in a range of 148.5 MHz~297 MHz, and each clock cycle allows 2 bits of data to be sent, that is, the data transmission rate is 297 Mbps to 594 MHz.

IV. Digital HD LCD TV Structure

1. TV motherboard:

         (1) PC smallboard (only for display with no TV function)

         (2) Traditional TV board (only TV function available with no networking)

         (3) Smart TV motherboard (with system available for networking)

2. Common interfaces from TCON board to LCD source board (side bar): mini-lvds, usi-t

3. Interfaces from mainboard to TCON board: 1080P 7:1 LVDS, V-by-one  

4. Non-common interfaces: CMPI (some 4k TV screens), EPI (some 4k TV screens), mipi (small size HD screens such as cell phone screens), RSDS (low-resolution screens), TTL (small-size low-resolution LCDs)